In a spectrum spread communication based on a code division multiplex access (CDMA) system which has been studied for use in the portable telephone or the like, a matched filter is used when a spectrum spread signal is demodulated to an original narrow-band signal (for example, "LSI, 110 mw for Digital Portable Telephone CDMA and Reduction of Consumption Power", Nikkei Electronics, No. 656, pp. 14-15, February, 1996).
FIG. 1 is a block diagram showing a conventional example of an eight-times spread 8-order digital matched filter constructed by using a FIR digital filter (for example, "Spectrum Spread Handbook Edition No. 4", Stanford Telecom Inc., 1996). A transfer function H(z) of this digital matched filter is expressed by the following equation. EQU H(z)=C.sub.0 +C.sub.1 Z.sup.-1 +C.sub.2 Z.sup.-2 +C.sub.3 Z.sup.-3 ++C.sub.4 Z.sup.-4 +C.sub.5 Z.sup.-5 +C.sub.6 Z.sup.-6 +C.sub.7 Z.sup.-7 (1)
This digital matched filter comprises a signal input terminal 1, a clock input terminal 2, a tapped shift register 10 including first to seventh flip-flop sets 11-17, first to eighth multipliers 21-28, first to seventh adders 31-37, and an output terminal 5. Here, each of the first to seventh flip-flop sets 11-17 constituting the tapped shift register 10 includes 6 flip-flops connected in parallel to each other.
A digital signal I.sub.o generated by sampling an analog signal (for example, a spectrum spread signal) at a sampling frequency of 4.096 MHz is inputted to the signal input terminal 1. The digital signal I.sub.o is a 6-bit digital signal in terms of two's complement that is synchronous with a clock CLK of 4.096 MHz inputted to the clock input terminal 2. The digital signal I.sub.o is applied to the first flip-flop set 11 of the tapped shift register 10, and then is sequentially shifted from the first flip-flop set 11 toward the seventh flip-flop set 17 in synchronism with the clock CLK.
Each of the first to eighth multipliers 21-28 is a multiplier for 6 bits.times.1 bit, and outputs an output signal of 6 bits. In the first multiplier 21, multiplication of the digital signal I.sub.o (6 bits) by a despreading code C.sub.0 (1 bit) of an 8-bit despreading code sequence C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.o is carried out. In the second to eighth multipliers 22-28, multiplication operations of output signals of the first to seventh flip-flop sets 11-17 by the despreading codes C.sub.1 -C.sub.7 are carried out, respectively.
For example, when the despreading code indicates "0", the multiplication operations of the digital signal I.sub.o and the output signals of the first to seventh flip-flop sets 11-17 by "-1" are carried out in the multipliers 21-28, respectively. When the despreading code indicates "1", the multiplication operations of the digital signal I.sub.o and the output signals of the first to seventh flip-flop sets 11-17 by "1" are carried out, respectively. The method of the multiplication operations in the multipliers 21-28 is not limited to this. For example, when the despreading code indicates "0", the multiplication operations of the digital signal I.sub.o and the output signals of the first to seventh flip-flop sets 11-17 by "1" may be carried out, respectively. When the despreading code indicates "1", the multiplication operations of the digital signal I.sub.o and the output signals of the first to seventh flip-flops 11-17 by "-1" may be carried out, respectively.
The procedure for the multiplication in each of the multipliers 21-28 will be described hereunder with reference to FIG. 2.
In the initial state, all of the output signals of the first to seventh flip-flop sets 11-17 constituting the tapped shift register 10 are rendered to be "0".
In the first operation state, a first sampling data D.sub.0 of the digital signal I.sub.o is inputted to the signal input terminal 1, and then the multiplication of the sampling data D.sub.0 by the despreading code C.sub.0 is carried out in the first multiplier 21. Accordingly, an output signal indicative of a value of D.sub.0.times.C.sub.0 is outputted from the first multiplier 21.
In the second operation state, a second sampling data D.sub.1 of the digital signal I.sub.o is inputted to the signal input terminal 1 in synchronism with the clock CLK, and the first sampling data D.sub.0 is fetched in the first flip-flop set 11. As a result, the multiplication of the second sampling data DI by the despreading code C.sub.0 is carried out in the first multiplier 21, and the multiplication of the first sampling data D.sub.0 by the despreading code C.sub.1 is carried out in the second multiplier 22. Accordingly, an output signal indicative of a value of D.sub.1.times.C.sub.0 is outputted from the first multiplier 21, and an output signal indicative of a value of D.sub.0.times.C.sub.1 is outputted from the second multiplier 22.
In the third operation state, a third sampling data D.sub.2 of the digital signal I.sub.o is inputted to the signal input terminal 1 in synchronism with the clock CLK, the first sampling data D.sub.0 is fetched in the second flip-flop set 12, and the second sampling data D.sub.1 is fetched in the first flip-flop set 11. As a result, the multiplication of the third sampling data D.sub.2 by the despreading code C.sub.0 is carried out in the first multiplier 21, the multiplication of the second sampling data D.sub.1 by the despreading code C.sub.1 is carried out in the second multiplier 22, and the multiplication of the first sampling data D.sub.0 by the despreading code C.sub.2 is carried out in the third multiplier 23. Accordingly, an output signal indicative of a value of D.sub.2.times.C.sub.0 is outputted from the first multiplier 21, an output signal indicative of a value of D.sub.1.times.C.sub.1 is outputted from the second multiplier 22, and an output signal indicative of a value of D.sub.0.times.C.sub.2 is outputted from the third multiplier 23. Subsequently, a similar operation is repeated until a seventh operation state.
In the eighth operation state, an eighth sampling data D.sub.7 of the digital signal I.sub.o is inputted to the signal input terminal 1 in synchronism with the clock CLK, and the first to seventh sampling data D.sub.0 -D.sub.6 are fetched in the seventh to first flip-flop sets 17-11, respectively. Accordingly, an output signal indicative of a value of D.sub.7.times.C.sub.0 is outputted from the first multiplier 21, an output signal indicative of a value of D.sub.6.times.C.sub.1 is outputted from the second multiplier 22, an output signal indicative of a value of D.sub.5.times.C.sub.2 is outputted from the third multiplier 23, an output signal indicative of a value of D.sub.4.times.C.sub.3 is outputted from the fourth multiplier 24, an output signal indicative of a value of D.sub.3.times.C.sub.4 is outputted from the fifth multiplier 25, an output signal indicative of a value of D.sub.2.times.Cs is outputted from the sixth multiplier 26, an output signal indicative of a value of D.sub.1.times.C.sub.6 is outputted from the seventh multiplier 27, and an output signal indicative of a value of D.sub.0.times.C.sub.7 is outputted from the eighth multiplier 28.
Through the above operation, the multiplication operations necessary to determine a correlation value between the initial 8 sampling data D.sub.0 -D.sub.7 of the digital signal I.sub.o and the 8-bit despreading code sequence C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0 are all carried out.
In the ninth operation state, a ninth sampling data D.sub.8 of the digital signal I.sub.o is inputted to the signal input terminal 1 in synchronism with the clock CLK, and the second to eighth sampling data D.sub.1 -D.sub.7 are fetched in the seventh to first flip-flop sets 17-11, respectively. Accordingly, an output signal indicative of a value of D.sub.8.times.C.sub.0 is outputted from the first multiplier 21, an output signal indicative of a value of D.sub.7.times.C.sub.1 is outputted from the second multiplier 22, an output signal indicative of a value of D.sub.6.times.C.sub.2 is outputted from the third multiplier 23, an output signal indicative of a value of D.sub.5.times.C.sub.3 is outputted from the fourth multiplier 24, an output signal indicative of a value of D.sub.4.times.C.sub.4 is outputted from the fifth multiplier 25, an output signal indicative of a value of D.sub.3.times.C.sub.5 is outputted from the sixth multiplier 26, an output signal indicative of a value of D.sub.2.times.C.sub.6 is outputted from the seventh multiplier 27, and an output signal indicative of a value of D.sub.1.times.C.sub.7 is outputted from the eighth multiplier 28. As a result, the multiplication operations necessary to determine a correlation value of 8 sampling data D.sub.1 -D.sub.8, which are one sampling after the initial 8 sampling data D.sub.0 -D.sub.7 of the digital signal I.sub.o, and the 8-bit despreading code sequence C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0 are all carried out. Subsequently, a similar operation is repeated.
Each of the first to fourth adders 31-34 is an adder for 6 bits+6 bits, and outputs an output signal of 7 bits. Each of the fifth and sixth adders 35 and 36 is an adder for 7 bits+7 bits, and outputs an output signal of 8 bits. The seventh adder 37 is an adder for 8 bits+8 bits, and outputs an output signal of 9 bits. In the first adder 31, addition of the output signal (6 bits) of the first multiplier 21 and the output signal (6 bits) of the second multiplier 22 is carried out. In the second adder 32, addition of the output signal (6 bits) of the third multiplier 23 and the output signal (6 bits) of the fourth multiplier 24 is carried out. In the third adder 33, addition of the output signal (6 bits) of the fifth multiplier 25 and the output signal (6 bits) of the sixth multiplier 26 is carried out. In the fourth adder 34, addition of the output signal (6 bits) of the seventh multiplier 27 and the output signal (6 bits) of the eighth multiplier 28 is carried out. In the fifth adder 35, addition of the output signal (7 bits) of the first adder 31 and the output signal (7 bits) of the second adder 32 is carried out. In the sixth adder 36, addition of the output signal (7 bits) of the third adder 33 and the output signal (7 bits) of the fourth adder 34 is carried out. In the seventh adder 37, addition of the output signal (8 bits) of the fifth adder 35 and the output signal (8 bits) of the sixth adder 36 is carried out. As a result, a correlation value MFOUT between the digital signal I.sub.o and the despreading code sequence C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0 is obtained in the seventh adder 37, and is outputted to the outside through the output terminal 5.
Next, a digital matched filter used when a receiving signal is over-sampled will be described.
In a case where the receiving timing is detected by performing the correlation detection of the receiving signal in the portable telephone or the like, in order to improve the accuracy of the receiving timing detection, the receiving signal is usually m-times over-sampled in relation to a chip rate frequency, and then is inputted to the matched filter. When the receiving signal is doubly over-sampled, a transfer function H(z) is expressed by the following equation. EQU H(z)=C.sub.0 +C.sub.1 Z.sup.-2 +C.sub.2 Z.sup.-4 +C.sub.3 Z.sup.-6 ++C.sub.4 Z.sup.-8 +C.sub.5 Z.sup.-10 +C.sub.6 Z.sup.-12 +C.sub.7 Z.sup.-14 (2)
FIG. 3 is a block diagram showing a conventional example of an eight-times spread 16-order digital matched filter constructed by using an FIR 2-times over-sampling interpolation digital filter. The digital matched filter comprises a signal input terminal 101, a clock input terminal 102, a tapped shift register 110 including first to fourteenth flip-flop sets 111-124, first to eighth multipliers 131-138, first to seventh adders 141-147, and an output terminal 105. Here, each of the first to fourteenth flip-flop sets 111-124 constituting the tapped shift register 110 includes 6 flip-flops connected in parallel to each other.
A digital signal I.sub.o generated by doubly over-sampling an analog signal (for example, a spectrum spread signal) at a sampling frequency of 8.192 MHz is inputted to the signal input terminal 101. The digital signal I.sub.o is a 6-bit digital signal in terms of two's complement that is synchronous with a clock CLK of 8.192 MHz inputted to the clock input terminal 102. The digital signal I.sub.o is applied to the first flip-flop set 111 of the tapped shift register 110, and then is sequentially shifted from the first flip-flop set 111 toward the fourteenth flip-flop set 124 in synchronism with the clock CLK.
Each of the first to eighth multipliers 131-138 is a multiplier for 6 bits.times.1 bit, and outputs an output signal of 6 bits. In the first multiplier 131, multiplication of the digital signal I.sub.o (6 bits) by a despreading code C.sub.0 (1 bit) of an 8-bit despreading code sequence C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0 is carried out. In the second to eighth multipliers 132-138, multiplication operations of output signals of the even flip-flop sets 112, 114, 116, 118, 120, 122 and 124 of the tapped shift register 110 by despreading codes C.sub.1 -C.sub.7 are carried out, respectively.
For example, when the despreading code indicates "0", the multiplication operations of the digital signal I.sub.o and the output signals of the even flip-flop sets 112, 114, 116, 118, 120, 122 and 124 by "-1" are carried out in the multipliers 131-138, respectively. When the despreading code indicates "1", the multiplication operations of the digital signal I.sub.o and the output signals of the even flip-flop sets 112, 114, 116, 118, 120, 122 and 124 by "1" are carried out, respectively. The method of multiplication in the multipliers 131-138 is not limited to this. For example, when the despreading code indicates "0", the multiplication operations of the digital signal I.sub.o and the output signals of the even flip-flop sets 112, 114, 116, 118, 120, 122 and 124 by "1" may be carried out, respectively. When the despreading code indicates "1", the multiplication operations of the digital signal I.sub.o and the output signals of the even flip-flop sets 112, 114, 116, 118, 120, 122 and 124 by "-1" may be carried out, respectively.
Each of the first to fourth adders 141-144 is an adder for 6 bits+6 bits, and outputs an output signal of 7 bits. Each of the fifth and sixth adders 145 and 146 is an adder for 7 bits+7 bits, and outputs an output signal of 8 bits. The seventh adder 147 is an adder for 8 bits+8 bits, and outputs an output signal of 9 bits. In the first adder 141, addition of the output signal (6 bits) of the first multiplier 131 and the output signal (6 bits) of the second multiplier 132 is carried out. In the second adder 142, addition of the output signal (6 bits) of the third multiplier 133 and the output signal (6 bits) of the fourth multiplier 134 is carried out. In the third adder 143, addition of the output signal (6 bits) of the fifth multiplier 135 and the output signal (6 bits) of the sixth multiplier 136 is carried out. In the fourth adder 144, addition of the output signal (6 bits) of the seventh multiplier 137 and the output signal (6 bits) of the eighth multiplier 138 is carried out. In the fifth adder 145, addition of the output signal (7 bits) of the first adder 141 and the output signal (7 bits) of the second adder 142 is carried out. In the sixth adder 146, addition of the output signal (7 bits) of the third adder 143 and the output signal (7 bits) of the fourth adder 144 is carried out. In the seventh adder 147, addition of the output signal (8 bits) of the fifth adder 145 and the output signal (8 bits) of the sixth adder 146 is carried out.
In this digital matched filter, a correlation value MFOUT between the digital signal I.sub.o and the despreading code sequence C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0 is obtained in the seventh adder 147, and is outputted to the outside through the output terminal 105, too. In the digital matched filter, the correlation value MFOUT can be obtained each time that the clock CLK of 8.192 MHz is inputted to the clock input terminal 102, so that the correlation value MFOUT can be obtained at a time interval which is half the time interval in the digital matched filter shown in FIG. 1.
However, the conventional digital matched filters shown in FIGS. 1 and 3 face a fatal problem that consumption power is large. Namely, in the conventional digital matched filter shown in FIG. 1, in order to obtain the correlation value MFOUT between the digital signal I.sub.o and the despreading code sequence C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0 the tapped shift register 10 including the first to seventh flip-flop sets 11-17 is used as a tapped delay line unit. As a result, the tapped shift register 10 is operated in synchronism with the clock CLK of 4.096 MHz, so that consumption power increases. In the conventional digital matched filter shown in FIG. 3, in order to obtain the correlation value MFOUT between the digital signal I.sub.o and the despreading code sequence C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0, the tapped shift register 110 including the first to fourteenth flip-flop sets 111-124 is used as a tapped delay line unit. As a result, the tapped shift register 110 is operated in synchronism with the clock CLK of 8.192 MHz, so that consumption power further increases.
In the correlation detector for the correlation detection of the spectrum spread signal in the portable telephone or the like, the correlation detection needs to be carried out for the in-phase channel and the quadrature channel, so that the correlation detector needs to be constructed by using two of the conventional digital matched filters as above. As a result, the correlation detector is constructed by using the conventional digital matched filters shown in FIG. 1 or 3, raising a problem that consumption power in the correlation detector is increased. In addition, there arises a problem that the consumption power in the correlation detector increases in proportion to an increase in the bit number of digital signal, an increase in the tap number of shift register and an increase in the number of interpolation processes.
In order to reduce the consumption power in the correlation detector, a matched filter for wide-band DS-CDMA fundamentally constructed on the basis of an analog/digital filter for performing the correlation detection through the analog signal processing has been developed (Sawahashi et al, "Low Power Consumption Matched Filter LSI for Wideband DS-CDMA", Technical Study Report of the Institute of Electronic Information Communication (Radio Communication), RCS95-120, January, 1996). The matched filter for wide-band DS-CDMA, however, uses a tapped delay unit including a plurality of sample-hold circuits inputted with an analog input signal, and a plurality of multiplication circuits for performing multiplication operations of respective output signals of the tapped delay unit by a multiplicator represented by a digital signal. Therefore, in a utilization such as the portable telephone of the spectrum spread communication system in which the digital signal processing predominantly proceeds, a digital matched filter which is totally constructed with digital circuits can be integrated more easily with peripheral circuits for digital signal processing.
Also, U.S. Pat. No. 5,396,446 discloses a digital filter circuit comprising a plurality of hold circuits which are respectively inputted with an input signal, a recursive tapped shift register for storing multiplicators, a plurality of multipliers for multiplying output signals of the plurality of hold circuits by output signals of the recursive tapped shift register, respectively, and an adder for adding output signals of the plurality of multipliers. However, the digital filter circuit is not devised with the aim of reducing consumption power as compared to the conventional digital matched filter using the tapped shift register as the tapped delay unit, but is devised with the aim of suppressing the hold error to a minimum by constructing the hold circuit through the use of two differential amplifiers, two transistors and two capacitors and controlling conduction/non-conduction of the two transistors with clocks which are in opposite phase with each other. Further, in the digital filter circuit, input data is cumulated and held in the capacitor of each hold circuit, so that the accuracy of holding the input data is degraded as compared to a case where input data is held by a digital circuit. Further, in the digital filter circuit, the hold circuit, the multiplier and the adder are constructed by using analog elements such as capacitors. Therefore, in the utilization such as the portable telephone of the spectrum spread communication system in which the digital signal processing predominantly proceeds, the digital matched filter which is totally constructed with digital circuits can be integrated more easily with peripheral circuits for digital signal processing.